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dsPIC33FJXXXGPXXX/ DSPIC33FJXXXMCXXX
dsPIC33F Rev. A2 Silicon Errata
dsPIC33FJXXXGPXXX, DSPIC33FJXXXMCXXX (Rev. A2) Silicon Errata
The dsPIC33F devices (Rev. A2) you received were found to conform to the specifications and functionality described in the following documents: * DS70165 - "dsPIC33F Family Data Sheet" * DS70157 - "dsPIC30F/33F Programmer's Reference Manual" * DS70046 - "dsPIC30F Family Reference Manual" The exceptions to the specifications in the documents listed above are described in this section. The specific devices for which these exceptions are described are listed below: * * * * * * * * * * * * * * * * * * * * * * * * * * * dsPIC33FJ64GP206 dsPIC33FJ64GP306 dsPIC33FJ64GP310 dsPIC33FJ64GP706 dsPIC33FJ64GP708 dsPIC33FJ64GP710 dsPIC33FJ128GP206 dsPIC33FJ128GP306 dsPIC33FJ128GP310 dsPIC33FJ128GP706 dsPIC33FJ128GP708 dsPIC33FJ128GP710 dsPIC33FJ256GP506 dsPIC33FJ256GP510 dsPIC33FJ256GP710 dsPIC33FJ64MC506 dsPIC33FJ64MC508 dsPIC33FJ64MC510 dsPIC33FJ64MC706 dsPIC33FJ64MC710 dsPIC33FJ128MC506 dsPIC33FJ128MC510 dsPIC33FJ128MC706 dsPIC33FJ128MC708 dsPIC33FJ128MC710 dsPIC33FJ256MC510 dsPIC33FJ256MC710 dsPIC33F Rev. A2 silicon is identified by performing a "Reset and Connect" operation to the device using MPLAB(R) ICD 2 with MPLAB IDE v7.40 or later. The output window will show a successful connection to the device specified in Configure>Select Device. The errata described in this section will be addressed in future revisions of silicon.
Silicon Errata Summary
The following list summarizes the errata described in further detail through the remainder of this document: 1. Doze Mode When Doze mode is enabled, any writes to a peripheral SFR can cause other updates to that register to cease to function for the duration of the current CPU clock cycle. 2. 12-bit Analog-to-Digital Converter (ADC) Module For this revision of silicon, the 12-bit ADC module INL, DNL and signal acquisition time parameters are not within the published data sheet specifications. 3. 10-bit ADC Module For this revision of silicon, the 10-bit ADC module DNL, conversion speed and signal acquisition time parameters are not within the published data sheet specifications. 4. DMA Module: Interaction with EXCH Instruction The EXCH instruction does not execute correctly when one of the operands contains a value equal to the address of the DMAC SFRs. 5. DISI Instruction The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the DISI counter decrements to zero. 6. Motor Control PWM There is a glitch in the PWMxL signal in SingleShot mode with complementary output. Another glitch occurs when resuming from a Fault condition in Free-Running mode with complementary output.
(c) 2006 Microchip Technology Inc.
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dsPIC33F
7. Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 8. Output Compare Module in PWM Mode The output compare module will miss one compare event when the duty cycle register value is updated from 0x0000 to 0x0001. 9. SPI Module in Frame Master Mode The SPI module will fail to generate frame synchronization pulses in Frame Master mode. 10. SPI Module in Slave Select Mode The SPI module Slave Select functionality will not work correctly. 11. SPI Module The SMP bit does not have any effect when the SPI module is configured for a 1:1 prescale factor in Master mode. 12. ECANTM Module ECAN transmissions may be incorrect if multiple transmit buffers are simultaneously queued for transmission. 13. ECAN Module Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer ID register. 14. ECAN Module Loopback Mode The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode. 15. I2CTM Module The bus collision status bit does not get set when a bus collision occurs during a Restart or Stop event. 16. INT0, ADC and Sleep/Idle Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero. 17. Doze Mode and Traps The address error trap, stack error trap, math error trap and DMA error trap will not wake-up a device from Doze mode. 18. JTAG Programming JTAG programming does not work. The following sections will describe the errata and work around to these errata, where they may apply.
1. Module: Oscillator: Doze Mode
Enabling Doze mode slows down the CPU but allows peripherals to run at full speed. When the CPU clock is slowed down by enabling Doze mode (CLKDIV<11> = 1), any writes to a peripheral SFR can cause other updates to that register to cease to function for the duration of the current CPU clock cycle. This is only an issue if the CPU attempts to write to the same register as a peripheral while in Doze mode. For instance, if the ADC module is active and Doze mode is enabled, the main program should avoid writing to ADCCONx registers because these registers are being used by the ADC module. If the CPU does make writes before the ADC module does, then any attempts by the ADC module to write to these registers will fail. Work around In Doze mode, avoid writing code that will modify SFRs which may be written to by enabled peripherals.
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(c) 2006 Microchip Technology Inc.
dsPIC33F
2. Module: 12-bit ADC
When the ADC module is configured for 12-bit operation, the specifications in the data sheets are not met. Work around Implement the ADC module as an 11-bit ADC with a maximum conversion rate of 300 Ksps. 1. The specifications provided below reflect 11-bit ADC operation. RIN source impedance is recommended as 200 ohms and sample time is recommended as 3 TAD to ensure compatibility on future enhanced ADC modules. Missing codes are possible every 27 codes. 2. When used as a 10-bit ADC, the INL is <2 LSBs, and DNL is <1 LSB with no missing codes. Maximum conversion rate is 300 Ksps.
TABLE 1:
Param No. AD17 AD20a AD21a AD22a AD23a AD24a AD21aa AD22aa AD23aa AD24aa AD33a AD34a AD56a AD57a
ADC PERFORMANCE (11-BIT OPERATION)
Symbol RIN Nr INL DNL GERR EOFF INL DNL GERR EOFF FNYQ ENOB FCNV TSAMP Min -- -- -2 -1.5 1 1 -2 -1.5 5 3 -- 9.5 -- -- Typical -- 12 bits -- -- 5 3 -- -- 10 6 -- 9.6 -- 3 TAD Max 200 -- 2 1 10 6 2 1 20 15 150 10.4 300 -- Units Ohm Bits LSB LSB LSB LSB LSB LSB LSB LSB KHz Bits Ksps -- Conditions 12-bit
ADC Accuracy - Measurements taken with External VREF+/VREF-
ADC Accuracy - Measurements taken with Internal VREF+/VREF-
Dynamic Performance
ADC Conversion Rate
(c) 2006 Microchip Technology Inc.
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3. Module: 10-bit ADC
When the ADC module is configured for 10-bit operation, the specifications in the data sheet are not met for operation above 500 Ksps. For 500 Ksps, the module meets specifications except for Gain and Offset parameters AD23bb and AD24bb. For 600 Ksps operation, the module specifications are shown in Table 2. Work around None. Future versions of the silicon will support the ADC performance stated in the data sheet.
TABLE 2:
Param No. AD17 AD20b AD21b AD22b AD23b AD24b AD21bb AD22bb AD23bb AD24bb AD33b AD34b AD56b AD57b
600 KSPS OPERATION
Symbol RIN Nr INL DNL GERR EOFF INL DNL GERR EOFF FNYQ ENOB FCNV TSAMP Min -- -- -2 -1.5 1 1 -2 -1.5 1 2 -- 8.5 -- -- Typ -- 10 bits -- -- 3 2 -- -- 6 5 Dynamic Performance -- 9.7 ADC Conversion Rate -- 3 TAD 600 -- Ksps -- 300 9.8 KHz Bits Max 200 -- 2 2 6 5 2 2 12 10 Units Ohm Bits LSB LSB LSB LSB LSB LSB LSB LSB Conditions 10-bit
ADC Accuracy - Measurements taken with External VREF+/VREF-
ADC Accuracy - Measurements taken with Internal VREF+/VREF-
4. Module: DMA Module: Interaction with EXCH Instruction
The EXCH instruction does not execute correctly when either of the two operands is numerically equal to the address of any of the DMAC SFRs for this revision of silicon. Work around If writing source code in assembly, the recommended fix is to replace: EXCH Wsource, Wdestination with: PUSH Wdestination MOV Wsource, Wdestination POP Wsource
If using the MPLAB C30 C compiler, check the disassembly listing (View>Disassembly Listing) for the EXCH instruction. If used, make sure the operands are not equivalent to the DMA SFRs' addresses.
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(c) 2006 Microchip Technology Inc.
dsPIC33F
5. Module: DISI Instruction
When a user executes a DISI #7, for example, this will disable interrupts for 7 + 1 cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from 7 to 0. The counter is loaded with 7 at the end of the DISI instruction. If the user code executes another DISI on the instruction cycle where the DISI counter has become zero, the new DISI count is loaded, but the DISI state machine does not properly reengage and continue to disable interrupts. At this point, all interrupts are enabled. The next time the user code executes a DISI instruction, the feature will act normally and block interrupts. In summary, it is only when a DISI execution is coincident with the current DISI count = 0, that the issue occurs. Executing a DISI instruction before the DISI counter reaches zero will not produce this error. In this case, the DISI counter is loaded with the new value, and interrupts remain disabled until the counter becomes zero. Work around When executing multiple DISI instructions within the source code, make sure that subsequent DISI instructions have at least one instruction cycle between the time that the DISI counter decrements to zero and the next DISI instruction. Alternatively, make sure that subsequent DISI instructions are called before the DISI counter decrements to zero.
7. Module: Output Compare Module
A glitch will be produced on an output compare pin under the following conditions: * The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register. * The output compare module is configured and enabled to drive the pin low at some later time (OCxCON = 0x0002 or OCxCON = 0x0003). When these events occur, the output compare module will drive the pin low for one instruction cycle (TCY) after the module is enabled. Work around None. However, the user may use a timer interrupt and write to the associated PORT register to control the pin manually.
8. Module: Output Compare Module in PWM Mode
The output compare module will miss a compare event when the current duty cycle register (OCxRS) value is 0x0000 (0% duty cycle) and the OCxRS register is updated with a value of 0x0001. The compare event is missed only the first time a value of 0x0001 is written to OCxRS, and the PWM output remains low for one PWM period. Subsequent PWM high and low times occur as expected. Work around None. If the current OCxRS register value is 0x0000, avoid writing a value of 0x0001 to OCxRS. Instead, write a value of 0x0002; however, in this case the duty cycle will be slightly different from the desired value.
6. Module: Motor Control PWM
Devices in the motor control family have a glitch in the PWMxL signal under certain conditions. The glitch is a brief high pulse during the low portion of the duty cycle. This error occurs when the module is configured in Single-Shot mode (PTMOD<1:0> = 01) with complementary output. It also occurs when resuming from a Fault condition in Free-Running mode (PTMOD<1:0) = 00) with complementary output. Work around None.
(c) 2006 Microchip Technology Inc.
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9. Module: SPI Module in Frame Master Mode
The SPI module will fail to generate frame synchronization pulses when configured in the Frame Master mode (FRMEN = 1, SPIFSD = 0). However, the module functions correctly in Frame Slave mode. Work around If DMA is not being used, manually drive the SSx pin (x = 1 or 2) high using the associated PORT register, and then drive it low after the required 1 bit-time pulse width. This operation needs to be performed when the transmit buffer is written. If DMA is being used, and if no other peripheral modules are using DMA transfers, use a timer interrupt to periodically generate the frame synchronization pulse (using the method described above) after every 8 or 16 bit periods (depending on the data word size, configured using the MODE16 bit).
12. Module: ECAN Module
If multiple ECAN transmit buffers are queued for transmission (multiple TXREQ bits are set to `1' simultaneously), then the message transmissions from the enabled buffers may interfere with one another. As a result, incorrect ID and data transmissions will occur intermittently. Work around Enable only one transmit buffer for transmission at any given time. In the user application, this can be ensured by checking that all other TXREQn bits are clear before setting the TXREQn bit corresponding to the buffer that is to be transmitted.
13. Module: ECAN Module
Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer SID. If the ECAN module detects a Start-of-Frame (SOF) in the third bit of interframe space and if a message to be transmitted is pending, the first five bits of the transmitted identifier may be corrupted. Work around None.
10. Module: SPI Module in Slave Select Mode
The SPI module Slave Select functionality (enabled by setting SSEN = 1) will not function correctly. Whether the SSx pin (x = 1 or 2) is high or low, the SPI data transfer will be completed and an interrupt will be generated. Work around If DMA is not being used, manually poll the SSx pin state in the SPI interrupt by reading the associated LAT bit: * If the LAT bit is `0', then perform the required data read/write. * If the LAT bit is `1', then clear the SPI interrupt flag (SPIxIF), perform a dummy read of the SPIxBUF register, and return from the Interrupt Service Routine. If DMA is being used, there is no work around.
14. Module: ECAN Module Loopback Mode
The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode. Work around Do not use Loopback mode.
15. Module: I2C Module
The Bus Collision Status bit (BCL) does not get set when a bus collision occurs during a Restart or Stop event. However, the BCL bit gets set when a bus collision occurs during a Start event. Work around None.
11. Module: SPI Module
The SMP bit (SPIxCON1<9>, where x = 1 or 2) does not have any effect when the SPI module is configured for a 1:1 prescale factor in Master mode. In this mode, whether the SMP bit is set or cleared, the data is always sampled at the end of data output time. Work around If sampling at the middle of data output time is required, then configure the SPI module to use a clock prescale factor other than 1:1 using the PPRE<1:0> and SPRE<2:0> bits in the SPIxCON1 register.
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(c) 2006 Microchip Technology Inc.
dsPIC33F
16. Module: INT0, ADC and Sleep/Idle Mode
ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate an interrupt after a certain number of INT0 triggered conversions, the ADC conversions will not be triggered and the device will remain in Sleep. The ADC will perform conversions and wake-up the device only if it is configured to generate an interrupt after each INT0 triggered conversion (SMPI<3:0> = 0000). Work around None. If ADC event trigger from the INT0 pin is required, initialize SMPI<3:0> to `0000' (interrupt on every conversion).
17. Module: Doze Mode and Traps
The address error trap, stack error trap, math error trap and DMA error trap will not wake-up a device from Doze mode. Work around None.
18. Module: JTAG Programming
JTAG programming does not work. Work around None.
(c) 2006 Microchip Technology Inc.
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dsPIC33F
APPENDIX A:
Revision A (6/2006) * Initial release of the document. Revision B (12/2006) * Added errata 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17.
REVISION HISTORY
DS80279B-page 8
(c) 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2006 Microchip Technology Inc.
DS80279B-page 9
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS80279B-page 10
(c) 2006 Microchip Technology Inc.

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